The Chameleon project in retrospective

In this paper we describe in retrospective the main results of a four year project, called Chameleon. As part of this project we developed a coarse-grained reconfigurable core for DSP algorithms in wireless devices denoted MONTIUM. After presenting the main achievements within this project we present the lessons learned from this project

Lessons Learned from Designing the Montium - a Coarse-Grained Reconfigurable Processing Tile

In this paper we describe in retrospective the main results of a four year project, called Chameleon. As part of this project we developed a coarse-grained reconfigurable core for DSP algorithms in wirelessdevices denoted MONTIUM. After presenting the main achievements within this project we present the lessons learned from this project

The SmartCulTour Toolkit.

Deliverable 7.3 of the Horizon 2020 project SmartCulTour (GA number 870708), published on theproject web site on (30-11-2022): http://www.smartcultour.eu/deliverables

The SmartCulTour Toolkit.

Deliverable 7.3 of the Horizon 2020 project SmartCulTour (GA number 870708), published on theproject web site on (30-11-2022): http://www.smartcultour.eu/deliverables

Designing destinations for good: Using design roadmapping to support pro-active destination development.

This conceptual paper develops and justifies a pro-active, design-driven approach to sustainable destination development. Using insights from design science, it helps explain the limited practical usability of concepts such as the Tourism Area Life Cycle, by noting that these often focus on an aggregated ‘topological’ level of destination design, while a focus on experiences and product development on a ‘typological’ and ‘morphological’ level is key to constitute change. The ‘Tourism Destination Design Roadmap’ is introduced, its potential to scrutinise ‘visitor flows’ is explored as well as ways in which it can contribute to developing desirable qualities in a destination, while minimising negative impacts. The paper concludes by highlighting its conceptual contribution and identifying directions for future research.</p

On hardware for generating routes in Kautz digraphs

In this paper we present a hardware implementation of an algorithm for generating node disjoint routes in a Kautz network. Kautz networks are based on a family of digraphs described by W.H. Kautz[Kautz 68]. A Kautz network with in-degree and out-degree d has N = dk + dk¿1 nodes (for any cardinals d, k>0). The diameter is at most k, the degree is fixed and independent of the network size. Moreover, it is fault-tolerant, the connectivity is d and the mapping of standard computation graphs such as a linear array, a ring and a tree on a Kautz network is straightforward.\ud The network has a simple routing mechanism, even when nodes or links are faulty. Imase et al. [Imase 86] showed the existence of d node disjoint paths between any pair of vertices. In Smit et al. [Smit 91] an algorithm is described that generates d node disjoint routes between two arbitrary nodes in the network. In this paper we present a simple and fast hardware implementation of this algorithm. It can be realized with standard components (Field Programmable Gate Arrays)